DocumentCode
2380724
Title
A Flexible Design Flow for a Low Power RFID Tag
Author
Palma, José C S ; Marcon, César ; Hessel, Fabiano ; Bezerra, Eduardo ; Rohde, Guilherme ; Azevedo, Luciano ; Reif, Carlos ; Metzler, Carolina
Author_Institution
PPGC - II - UFRGS - Av. Bento Gonçalves, 9500, Porto Alegre, RS - Brazil
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
300
Lastpage
303
Abstract
This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.
Keywords
Costs; Electromagnetic scattering; Energy consumption; ISO standards; Passive RFID tags; Power supplies; Power system security; RFID tags; Radio frequency; Radiofrequency identification; RFID Systems; Tag customization; low power consumption.;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location
Atlanta, GA, USA
Print_ISBN
978-1-4244-1710-0
Electronic_ISBN
978-1-4244-1710-0
Type
conf
DOI
10.1109/VLSISOC.2007.4402517
Filename
4402517
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