Efficient timing closure with a transistor level design flow

This paper presents a new transistor level design flow where it is possible to optimize the circuit with a wide number of logic functions and drive strengths. Different from the standard cell approach, our methodology is not limited to a previously characterized library of cells. The proposed design flow provides a virtual library with around 15,000 cells for logic synthesis and performs a transistor sizing optimization step to improve the timing of the circuit during layout generation. A transistor-level layout generator allows to explore these wide number of cells and drive strengths while optimizing the layout concerning connections and transistors. Circuits generated by our methodology were compared to the standard cell approach in which presented around 11 % of delay improvement and more than 30% of power savings.