DocumentCode
2380793
Title
A 4 Gsample/s 8b ADC in 0.35 /spl mu/m CMOS
Author
Poulton, K. ; Neff, R. ; Muto, A. ; Wei Liu ; Burstein, A. ; Heshami, M.
Author_Institution
Agilent Technol., Palo Alto, CA, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
166
Abstract
A 4 Gsample/s 8b ADC in 0.35 /spl mu/m CMOS achieves accuracy of 7 effective bits at DC and 6.1 effective bits for 1 GHz input, while dissipating 4.6 W. It uses 32 current-mode pipelines driven by 32 interleaved clocks with 1.1 ps RMS accuracy.
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; integrated circuit measurement; pipeline processing; 0.35 micron; 1 GHz; 4.6 W; 8 bit; ADC accuracy; CMOS ADC; current-mode pipelines; effective bit accuracy; interleaved clocks; power dissipation; CMOS technology; Capacitors; Circuits; Clocks; Delay; FETs; MOS devices; Pipelines; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992988
Filename
992988
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