Title :
A diagonal-interconnect architecture and its application to RISC core design
Author :
Igarashi, M. ; Mitsuhashi, T. ; Le, A. ; Kazi, S. ; Yang-Trung Lin ; Fujimura, A. ; Teig, S.
Author_Institution :
Toshiba Corp., Tokyo, Japan
Abstract :
Applying a design methodology based on an interconnect architecture characterized by pervasive use of diagonal wiring to a 128 b RISC processor core design results in 19.8 % path delay reduction and 10 % area reduction, compared to the conventional orthogonal interconnect architecture.
Keywords :
circuit layout CAD; delays; large scale integration; logic CAD; printed circuit layout; reduced instruction set computing; LSI feature; RISC processor core design; diagonal wiring; interconnect architecture; interconnect delay; miniaturization; orthogonal interconnect architecture; Delay; Design methodology; Integrated circuit interconnections; Large scale integration; Libraries; Pins; Reduced instruction set computing; Routing; Wire; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993010
