Load network design technique for microwave class-F amplifier

This paper presents the methodic design of the load network for class-F power amplifier (PA) with additional 3^rd and 5^th harmonics. The recommended load network equalizes the negative impact of the parasitic elements of the transistor (output capacity C_OUT and output inductance L_OUT) on the performance of class-F power amplifier. The technique reduces the negative impact of the actual effects of the shunt capacitor C_BYPASS in the supply circuit and blocking capacitor C_DCBLOCK on the impedance created by the load network on the transistor chip. According to the given technique, we have designed class-F power amplifier adding the 3^rd and 5^th harmonics onto the operating frequency 1.6 GHz using the gallium nitride (GaN) transistor CGH60008D. Drain efficiency (η_D) 80.17%, power-added efficiency (PAE) 78.11% and output power (_POUT) 38.9 dBm have been obtained through modeling on 1.6 GHz frequency.