A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

Author

Noguchi, H. ; Tateyama, T. ; Okamoto, M. ; Uchida, H. ; Kimura, M. ; Takahashi, K.

Author_Institution

Fiber Opt. Devices Div., NEC Corp., Kawasaki, Japan

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

252

Abstract

A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; demultiplexing equipment; jitter; optical communication equipment; optical fibre communication; semiconductor materials; synchronisation; voltage-controlled oscillators; wavelength division multiplexing; 0.5 micron; 1.45 W; 3.3 V; 9.9 to 10.8 Gbit/s; DC gain enhancer; DMUX; SiGe BiCMOS IC; WDM optical fiber transmission; dual-input voltage-controlled oscillator; external reference clock; fast/slow tracking loop; jitter generation; jitter tolerance; power dissipation; rate-adaptive clock-recovery; rate-adaptive data-recovery; Circuits; Clocks; Forward error correction; Frequency; Jitter; Optical fibers; Phase noise; Tracking loops; Voltage-controlled oscillators; Wavelength division multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993031

Filename

993031