Title :
An integrated 9-channel time digitizer with 30 ps resolution
Author :
Mantyniemi, A. ; Rahkonen, T. ; Kostamovaara, J.
Author_Institution :
Dept. of Electr. Eng., Oulu Univ., Finland
Abstract :
An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delay lines; interpolation; signal resolution; 0.6 micron; 50 mW; 66 MHz; CMOS integration; clock period bins; delay elements; integrated multi-channel time digitizer; power consumption; signal resolution; three-stage delay line interpolation/delay-generation principle; Clocks; Counting circuits; Delay effects; Delay lines; Flip-flops; Interpolation; Signal resolution; Synchronization; Time measurement; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993038
