DocumentCode
2381806
Title
Adaptive biasing of a 5.8 GHz CMOS oscillator
Author
Hitko, D.A. ; Sodini, C.G.
Author_Institution
Microsystems Technol. Lab., MIT, Cambridge, MA, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
292
Abstract
A key concept for VCOs in next-generation RF links is to allow phase noise performance to be scaled back to save power in times of reduced demand. A 5.8 GHz VCO and biasing circuitry in a 0.5 μm CMOS process have a performance adjustable from -107 dBc/Hz (1 MHz offset) with 6.2 mW dissipated to -121 dBc/Hz using 70 mW.
Keywords
CMOS analogue integrated circuits; MMIC oscillators; circuit tuning; field effect MMIC; integrated circuit noise; phase noise; voltage-controlled oscillators; 0.5 micron; 5.8 GHz; 6.2 to 70 mW; CMOS oscillator; VCO; adaptive biasing; next-generation RF links; onchip biasing circuitry; phase noise performance; tunable oscillator; CMOS technology; Circuits; Digital audio players; Mirrors; Operational amplifiers; Phase noise; Radio frequency; Tail; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993047
Filename
993047
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