Title :
A 30mW 12b 21MSample/s pipelined CMOS ADC
Author :
Kulhalli, S. ; Penkota, V. ; Asv, R.
Author_Institution :
Texas Instruments Inc., Bangalore, India
Abstract :
A 0.6/spl mu/m double-poly CMOS 12b ADC uses a number of different techniques to obtain low power. The ADC achieves 68dB SNR at 21 MSample/s, consuming 30mW at 2.7V. Die area is 2.56mm/sup 2/.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; 0.6 micron; 12 bit; 2.7 V; 30 mW; SNR; die area; double-poly CMOS; low power techniques; pipelined CMOS ADC; Capacitors; High power amplifiers; Instruments; Interleaved codes; Noise reduction; Parasitic capacitance; Pipelines; Power amplifiers; Preamplifiers; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993057
