DocumentCode
2381958
Title
A self-calibrated pipeline ADC with 200MHz IF-sampling frontend
Author
Waltari, M. ; Sumanen, L. ; Korhonen, T. ; Halonen, K.
Author_Institution
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
314
Abstract
A 13b 50MSample/s pipeline ADC with digital self-calibration and IF-sampling frontend, using a 0.35/spl mu/m BiCMOS process, achieves 76.5dB SFDR at 194MHz input. The chip occupies 6mm/sup 2/ and dissipates 715mW from a 2.9V supply.
Keywords
BiCMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; 0.35 micron; 13 bit; 194 MHz; 2.9 V; 200 MHz; 715 mW; BiCMOS process; IF-sampling frontend; SFDR; digital self-calibration; dynamic range; self-calibrated pipeline ADC; Bandwidth; Calibration; Capacitors; Circuit noise; Clocks; Nonlinear distortion; Pipelines; Sampling methods; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993058
Filename
993058
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