A 3 /spl mu/V-offset operational amplifier with 20 nV//spl radic/Hz input noise PSD at DC employing both chopping and autozeroing

Author

Tang, A.T.K.

Author_Institution

Analog Devices Inc., San Jose, CA, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

386

Abstract

A 3 /spl mu/V offset op-amp has been designed using both autozeroing and chopping to give 20 nV//spl radic/Hz input noise at DC with low energy at the chopping frequency. The design includes additional circuitry for reduced switching transients. Power consumption is 4 mW from a 5 V supply. Die area is 0.6/spl times/1.12 mm using a 0.6 /spl mu/m double-poly double-metal CMOS process.

Keywords

CMOS analogue integrated circuits; choppers (circuits); circuit noise; instrumentation amplifiers; operational amplifiers; transients; 0.6 micron; 0.6 mm; 1.12 mm; 3 muV; 4 mW; 5 V; DC input noise PSD; autozeroing; chip die area; chopping; chopping frequency; double-poly double-metal CMOS process; instrumentation amplifiers; op-amp input offset; operational amplifiers; power consumption; power spectral density; switching transients; Choppers; Circuit noise; Feedback circuits; Frequency; Low-frequency noise; Noise figure; Noise measurement; Operational amplifiers; Output feedback; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993094

Filename

993094