DocumentCode
2383257
Title
Challenges of electrostatic discharge (ESD) protection in silicon nanowire technology
Author
Liou, Juin J.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
fYear
2012
fDate
13-16 May 2012
Firstpage
11
Lastpage
13
Abstract
Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of modern and future integrated circuits, including the high-voltage, low-voltage, and emerging nanowire technologies.
Keywords
CMOS integrated circuits; electrostatic discharge; elemental semiconductors; failure analysis; integrated circuit reliability; nanowires; silicon; CMOS technology; ESD induced failures; ESD protection; Si; electrostatic discharge protection; integrated circuits; reliability; semiconductor industry; silicon nanowire technology; size 22 nm; CMOS integrated circuits; CMOS technology; Discharges (electric); Electrostatic discharges; Metals; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (MIEL), 2012 28th International Conference on
Conference_Location
Nis
ISSN
pending
Print_ISBN
978-1-4673-0237-1
Type
conf
DOI
10.1109/MIEL.2012.6222788
Filename
6222788
Link To Document