Implementation of FinFET based STT-MRAM bitcell

DGMOSFET or FinFET has emerged as a promising candidate to replace conventional MOSFET which suffers from various disadvantages like subthreshold leakage, gate-dielectric leakage, SCE (short-channel effect) or DIBL (drain-induced barrier lowering). Emerging technology like FinFET reduces these and improves variability. This paper presents a FinFET based STT-MRAM bitcell which is gaining researcher´s attention gradually by its nonvolatile nature and low power consumption. It proposes a 2-FinFETs, 1-MTJ based STT-MRAM bitcell to improve its performance metrics. Simulation results in HSPICE show that our proposed bitcell has less probability of read failure, write failure.