A low power adaptive bias fully differential operational amplifier

This article presents an adaptive bias class-AB operational amplifier (Op-Amp) which is designed such that all the transistors are operating in the sub-threshold region with very low power consumption. The basic objective of the design is to minimize a trade-off between slew rate and power consumption. To achieve high slew rate, an adaptive biasing circuit has been used which provides high dynamic current when the differential input voltage are applied and low quiescent current when common mode voltage applied. A common mode feed forward (CMFF) circuit has been used to get high CMRR which is very essential for reject the input signal common to both input terminal by making the output voltage free from the common mode input voltage. This proposed Op-Amp has been designed in BSIM3V3.1 0.18-μm CMOS technology. This Op-Amp gives 58-dB open-loop gain, 79.3-kHz unity-gain frequency, 74° phase margin, and 73.5-dB common-mode rejection ratio for 10-pF capacitive loads with 0.8V power supply. The proposed Op-Amp consumes 1.64 μW and provides slew rate of 0.14-V/μs.