Title :
The emergence & impact of DRAM-fab reuse in analog and power-management integrated circuits
Author :
Williams, Richard K. ; Cornell, Michael E.
Author_Institution :
Adv. Analogic Technol. Inc., Sunnyvale, CA, USA
Abstract :
Retrofitted with new, albeit unconventional, submicron-specific analog/power technologies, mid-to-deep submicron DRAM fab reuse offers significant and unexpected benefits in the performance, die size, and cost of analog mixed signal & power management ICs. New and novel devices and techniques including full-junction isolation without epitaxy, MeV chained-implant (CIJI) sidewall isolation, reduced lateral spacing (constrained implants and diffusions), hyper-accurate as-implanted DMOS channels, and new families of non-planar and trench-gated devices are now (for the first time) possible. A novel 0.35-μm epi-less ModularBCD process technology integrating fully-isolated CMOS; complementary bipolars; avalanche-capable lateral TrenchDMOS with independently optimized 5 V, 12 V and 30 V device arsenals is introduced. Building blocks including ultra-miniature (SC70-sized) 300 mA LDOs, 1-μsec (fast) current limiters, fast (10-MHz) fully-buffered power half-bridges (and more) exemplify the significant (and potentially revolutionary) size and performance gains of a submicron-specific analog/power technology approach to DRAM fab reuse.
Keywords :
CMOS integrated circuits; DRAM chips; analogue integrated circuits; current limiters; mixed analogue-digital integrated circuits; power integrated circuits; 0.35 micron; 1×10-6 sec; 10 MHz; 12 V; 30 V; 300 mA; 5 V; DRAM-fab reuse; MeV chained-implant sidewall isolation; analog integrated circuits; complementary bipolars; current limiters; full-junction isolation without epitaxy; fully-buffered power half-bridges; mid-to-deep submicron DRAM fab reuse; power-management integrated circuits; reduced lateral spacing; submicron-specific analog/power technologies; submicron-specific analog/power technology approach; Analog integrated circuits; CMOS technology; Costs; Disaster management; Energy management; Epitaxial growth; Integrated circuit technology; Isolation technology; Random access memory; Technology management;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2002. Proceedings of the 2002
Print_ISBN :
0-7803-7561-0
DOI :
10.1109/BIPOL.2002.1042884