DocumentCode :
238533
Title :
Agent-Based Memory Access for Many-Core CMPs
Author :
Weiwei Fu ; Mingmin Yuan ; Tianzhou Chen ; Li Liu
Author_Institution :
Coll. of Comput. Sci. & Technol., Zhejiang Univ. Hangzhou, Hangzhou, China
fYear :
2014
fDate :
24-27 June 2014
Firstpage :
43
Lastpage :
50
Abstract :
The trend of increasing on-chip core counts and integrating memory controllers (MCs) makes core-to-memory communication a major obstacle in scaling memory access performance for many-core CMPs. Unmanaged on-chip traffic for long-distance memory accesses, combined with information asymmetry between cores and remote MCs may lead to serious inefficiency in processing massive parallel memory accesses. In this paper we propose a novel agent-based memory access model for CMPs. We employ multiple agents inside the network to assist memory accesses to remote MCs, whose role lies in conducting memory requests from nearby cores, merging some repetitive memory requests and optimizing the scheduling under the backpressure of target MCs. We further describe a simple but effective case for agent-based memory access called Quad Agent, which deploys static agent modules in each quadrant of the network to serve requests towards MCs in other quadrants. The details of memory access merging, scheduling schemes and the architectural supports are discussed. Simulation results show that Quad Agent can reduce memory access latency by 13.3% on average and achieve 20.5% IPC speedup compared with the baseline. The performance promotion is due to increased memory access merge rate, row buffer hit rate and also prevention of traffic congestion and bank starvation.
Keywords :
multi-agent systems; multiprocessing systems; scheduling; storage management; MC; Quad Agent; agent-based memory access; architectural supports; bank starvation prevention; chip multiprocessing systems; core-to-memory communication; information asymmetry; many-core CMP; massive parallel memory access; memory access latency; memory access merge rate; memory access merging; memory controllers; on-chip core counts; row buffer hit rate; scheduling scheme; static agent modules; traffic congestion prevention; Distributed computing; Agent; Memory request merging; On-chip memory access traffic; Scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Computing (ISPDC), 2014 IEEE 13th International Symposium on
Conference_Location :
Marseilles
Print_ISBN :
978-1-4799-5918-1
Type :
conf
DOI :
10.1109/ISPDC.2014.9
Filename :
6900199
Link To Document :
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