The MasPar MP-1 architecture

Author

Blank, Tom

Author_Institution

MasPar Comput. Corp., Sunnyvale, CA, USA

fYear

1990

fDate

Feb. 26 1990-March 2 1990

Firstpage

20

Lastpage

24

Abstract

The MasPar MP-1 architecture is described. It is a massively parallel SIMD machine with the following key characteristics: scalable architecture in terms of the number of processing elements, system memory, and system communication bandwidth; reduced-instruction-set-computer-like instruction set design which leverages optimizing compiler technology; adherence to industry-standard floating point formats, specifically VAX and IEEE floating point; and an architectural design amenable to a VLSI implementation. The architecture provides not only high computational capability, but also a mesh and global interconnect style of communication. The computational model and subsystems of the MP-1, including the interconnection mechanisms, are described.<>

Keywords

parallel architectures; parallel machines; reduced instruction set computing; IEEE floating point; MasPar MP-1 architecture; RISC; VAX floating point; VLSI implementation; communication style; computational capability; computational model; global interconnect; industry-standard floating point formats; massively parallel SIMD machine; mesh interconnect; optimizing compiler technology; processing elements; reduced-instruction-set-computer-like instruction set design; scalable architecture; system communication bandwidth; system memory; Bandwidth; Broadcasting; Communication industry; Communication standards; Computer aided instruction; Computer architecture; Concurrent computing; Optimizing compilers; Process control; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2028-5

Type

conf

DOI

10.1109/CMPCON.1990.63648

Filename

63648