DocumentCode
2385517
Title
A universal structure for SRAM cell characterization
Author
Deng, Xiaowei ; Houston, Theodore W. ; Duong, Anhkim ; Loh, Wah Kit
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2010
fDate
22-25 March 2010
Firstpage
216
Lastpage
219
Abstract
A universal test structure (UTS) for SRAM cell characterization is proposed and implemented in 65nm - 28nm technologies. The structure allows, for the first time, measurement of nearly all transistor and cell characteristics of an SRAM cell on silicon. It hence enables direct correlation among various measured transistor and cell characteristics, collection of intra-bit transistor mismatch data, and assessment of wafer level Vmin sensitivity on transistor characteristics. Measured data are presented.
Keywords
SRAM chips; sensitivity analysis; silicon; transistors; SRAM cell characterization; cell characteristics; silicon; transistor characteristics; universal test structure; wafer level Vmin sensitivity assessment; CMOS technology; Driver circuits; MOSFETs; Microelectronics; Random access memory; Silicon; Testing; Time measurement; Variable structure systems; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location
Hiroshima
Print_ISBN
978-1-4244-6912-3
Electronic_ISBN
978-1-4244-6914-7
Type
conf
DOI
10.1109/ICMTS.2010.5466815
Filename
5466815
Link To Document