DocumentCode
2385533
Title
Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model
Author
Rideau, D. ; Quenette, V. ; Garetto, D. ; Dornel, E. ; Weybright, M. ; Manceau, J.P. ; Saxod, O. ; Tavernier, C. ; Jaouen, H.
Author_Institution
STMicroelectronics, Crolles, France
fYear
2010
fDate
22-25 March 2010
Firstpage
210
Lastpage
213
Abstract
This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.
Keywords
MOSFET; high-voltage techniques; leakage currents; technology CAD (electronics); TCAD simulations; gate-induced-drain-leakage; high voltage devices; low doped drain structures; overlap and fringing model; Doping profiles; Implants; Leakage current; Length measurement; MOS devices; MOSFETs; Performance evaluation; Semiconductor process modeling; Tunneling; Voltage; Leakage currents; MOSFETs; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location
Hiroshima
Print_ISBN
978-1-4244-6912-3
Electronic_ISBN
978-1-4244-6914-7
Type
conf
DOI
10.1109/ICMTS.2010.5466816
Filename
5466816
Link To Document