Title :
Compact models of parasitic resistance of resistors for analog circuits
Author_Institution :
Core Dev. Div., NEC Electron. Corp., Kawasaki, Japan
Abstract :
Accurate and useful compact models of parasitic resistance of resistors for analog circuits are proposed. The model is applicable to any layout patterns and topologies normally used in analog circuits. In addition, test structures to measure the parasitic resistance correctly are shown and the models are validated for a 40nm CMOS technology.
Keywords :
CMOS analogue integrated circuits; electric resistance measurement; integrated circuit layout; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; resistors; CMOS technology; analog circuit layout; compact model; parasitic resistance measurement; resistor; size 40 nm; test structures; Analog circuits; CMOS technology; Circuit testing; Contact resistance; Electrical resistance measurement; Estimation error; Immune system; Microelectronics; Resistors; Semiconductor device modeling; compact; model; parasitic; resistance; resistor;
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-6912-3
Electronic_ISBN :
978-1-4244-6914-7
DOI :
10.1109/ICMTS.2010.5466818
