Analog baseband receiver chip for 100 Mbps/1 Gbps broadband symmetric cable modem

The paper presents an analog baseband receiver chip on 1.2 μm SiGe bipolar process for 100 Mbps/1 Gbps symmetric ultra broadband modem (UBM) over CATV cable network. The chip is one of three chips transceiver chipset. This chip consists of 311 Msps slicers for data conversion, 155 MHz delay locked loop (DLL) for timing recovery, automatic gain control (AGC), slope detector for RF signal level conditioning, 155 MHz LVDS data and clock drivers for interfacing with digital ASIC, carrier and frame timing for carrier recovery and timing recovery, and serial interface with power control on a 4.4×4.4 mm² die with 64 pins TQFP package. The AGC circuit works with a RF VGA in a transmitter chip to provide more than 45 dB dynamic range. The slicers have a ping-pong scheme and are clocked at 311 Msps to work with digital ASIC at 1 Gbps data rate mode. The DLL recovers data timing for slicers and digital ASIC with 0.34° phase jitter. A bit error rate (BER) of 10^-12 has been measured at system level using this transceiver chipset.