Title :
A test structure for integrated capacitor array matching characterization
Author :
Posch, Werner ; Promitzer, Gilbert ; Seebacher, Ehrenfried
Author_Institution :
austriamicrosystems AG, Unterpremstaetten, Austria
Abstract :
A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations ¿(¿Ci / C) and the offsets ¿(¿Ci / C) of units i. Furthermore, the measurement repeatability is determined and an advanced derivation to consider the correlations introduced by the circuit structure and the extraction method is presented. The corresponding test chips were successfully realized in 0.35 um and 0.18 um standard CMOS technologies.
Keywords :
CMOS integrated circuits; MIM devices; capacitors; CMOS technology; MIM capacitor array; capacitor unit biasing; circuit structure; digital signal; extraction method; integrated capacitor array matching characterization; integrated capacitor array mismatch determination; measurement repeatability; size 0.18 mum; size 0.35 mum; spatial matching behavior; standard deviation; test chip; test structure; CMOS technology; Capacitance-voltage characteristics; Circuit testing; Digital control; Integrated circuit interconnections; MIM capacitors; Microelectronics; Parasitic capacitance; Signal generators; Switches; DFM; capacitance array; capacitance matching; capacitance mismatch; floating gate; matching; unit capacitors;
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-6912-3
Electronic_ISBN :
978-1-4244-6914-7
DOI :
10.1109/ICMTS.2010.5466833
