Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction techniques

This paper investigates leakage reduction techniques for a conventional 6T SRAM cell in advanced technologies. The most promising leakage reduction techniques that have been proposed are presented and compared for the 130-nm and 65-nm technology nodes. More specifically, the impact of the evolution of the gate tunneling and substrate currents is studied considering the efficiency of those techniques. Finally, the best techniques for leakage reduction in sub 100-nm SRAM cell, and guidelines on how to merge them in order to reach an optimum, are proposed