DocumentCode :
2386138
Title :
SIS wide-band model extraction methodology for SOI on-chip inductor
Author :
Topaloglu, Rasit Onur ; Goo, Jung-Suk ; Loke, Alvin L S ; Oshima, Michael M. ; Sim, Sam Wonsae
Author_Institution :
Globalfoundries, Sunnyvale, CA, USA
fYear :
2010
fDate :
22-25 March 2010
Firstpage :
90
Lastpage :
93
Abstract :
On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast modeling techniques are needed to enable low-cost and fast silicon turnaround. We present a fast and accurate methodology named scaled, iterative, and sampled (SIS) non-linear least squares optimization to extract wide-band model parameters suitable up to 20 GHz for inductor. To test our methodology, we implement a silicon-on-insulator (SOI) inductor in a 45 nm technology. The inductor is suitable for 8 to 20 GHz operation with 1.45 nH inductance and a quality factor of 17 at 10 GHz. We correlate our results to silicon measurements and achieve a very good fit between our models and silicon data. With our methodology, we achieve model-turnaround time of a few hours.
Keywords :
Q-factor; inductors; jitter; least squares approximations; oscillators; phase noise; silicon-on-insulator; SIS wideband model extraction methodology; SOI on-chip inductor; fast modeling technique; frequency 8 GHz to 20 GHz; jitter; nonlinear least squares optimization; oscillators; phase noise; quality factor; silicon-on-insulator inductor; size 45 nm; Inductors; Iterative methods; Jitter; Least squares methods; Optimization methods; Oscillators; Phase noise; Silicon on insulator technology; Testing; Wideband;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-6912-3
Electronic_ISBN :
978-1-4244-6914-7
Type :
conf
DOI :
10.1109/ICMTS.2010.5466850
Filename :
5466850
Link To Document :
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