Title :
Design and performance analysis of an output-buffering ATM switch with complexity of O(Nlog2N)
Author :
Awdeh, Ra´ed Y. ; Mouftah, H.T.
Author_Institution :
Dept. of Electr. Eng., Queen´´s Univ., Kingston, Ont., Canada
Abstract :
Despite their excellent performance, most existing output buffering ATM switches suffer from high implementation complexity. A deflection-routing ATM switch that achieves output buffering is described. The switch is based on multi-layering of single-stage interconnection networks. An analytical model for the performance evaluation of the switch is developed. It is shown that for arbitrary small cell loss probabilities, the complexity of the switch is of O(log 2N). Furthermore, the proposed switch is fair and preserves cell-sequencing. The switch is shown to compare well with some known ATM switch architectures
Keywords :
asynchronous transfer mode; buffer storage; computational complexity; electronic switching systems; hypercube networks; telecommunication network routing; O(Nlog2N) complexity; cell loss probabilities; cell-sequencing; deflection-routing ATM switch; design; multilayering; output-buffering ATM switch; performance analysis; single-stage interconnection networks; Analytical models; Asynchronous transfer mode; Distributed control; Fabrics; Hardware; Multiprocessor interconnection networks; Nonhomogeneous media; Performance analysis; Switches; Throughput;
Conference_Titel :
Communications, 1994. ICC '94, SUPERCOMM/ICC '94, Conference Record, 'Serving Humanity Through Communications.' IEEE International Conference on
Conference_Location :
New Orleans, LA
Print_ISBN :
0-7803-1825-0
DOI :
10.1109/ICC.1994.368868
