Optimal Design of Monolithic Integrated DC-DC Converters

Author

Schrom, G. ; Hazucha, P. ; Paillet, F. ; Gardner, D.S. ; Moon, S.T. ; Karnik, T.

Author_Institution

Intel Circuit Res. Lab., Hillsboro, OR

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

3

Abstract

Increasing supply current of high-performance microprocessors and limited real-estate available for power delivery in mobile platforms have spurred research of monolithic integrated DC-DC converters. Based on a model for the three key power loss mechanisms we derive an analytical solution for the optimal DC-DC converter design, linking power efficiency directly to CMOS front-end parameters and inductor technology. Further analysis shows that source-drain leakage, skin effect, eddy currents, and routing parasitics, although significant, don´t change the optimal design

Keywords

DC-DC power convertors; eddy currents; monolithic integrated circuits; CMOS front-end parameters; eddy currents; high-performance microprocessors; inductor technology; monolithic integrated DC-DC converters; power delivery; power loss mechanisms; routing parasitics; skin effect; source-drain leakage; CMOS technology; Current supplies; DC-DC power converters; Eddy currents; Inductors; Joining processes; Microprocessors; Routing; Semiconductor device modeling; Skin effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on

Conference_Location

Padova

Print_ISBN

1-4244-0097-X

Type

conf

DOI

10.1109/ICICDT.2006.220793

Filename

1669380