Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits

Three-dimensional integration (3DI) is a very promising fabrication methodology for extending the CMOS technology roadmap. As such, it is critical to evaluate the capability of this technique to provide reliable interconnection between stacked circuit layers. Since one of potential approaches for 3DI is through use of Cu bonded interconnects, the viability of this process is evaluated in this paper. More specifically, the integrity of bonded Cu interconnects has been investigated as a function of pattern geometry and density, as well as bonding process parameters. It is found that a pattern density around or more than 13 % coupled with the application of a small down-force (~1000 N) prior to temperature ramping and followed by large down-force (~10000 N) during bonding gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and thermal reliability. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology