A Seamless Ultra-Thin Chip Fabrication and Assembly Process

Various new applications of silicon technology, such as 3D circuit integration (Patti, 2006), system-on-chip (SoC), system-in-package (SiP), and electronics on foil or textile (Sanda et al.,2005), call for low-cost manufacturing and assembly of ultra-thin chips (5-50 mum). Practically all currently pursued concepts for fabricating thin chips are based on post-process thinning at wafer level, which, at thickness <50 mum, require application of a costly handle substrate. Also, grinding techniques applied to very thin wafers may lead to defect formation, thickness non-uniformity (wedging), and wafer fracture, thus causing yield loss and leading to high cost at this late stage of manufacture (Feil et al., 204). The paper proposed a new concept based on thin-chip fabrication by wafer pre-processing prior to the CMOS integration instead of post-process thinning of the entire wafer. There, the conventional chip dicing is replaced by a novel Pick, Crack & Placetrade process, through which the thin chip fabrication and assembly processes are seamlessly connected