DocumentCode :
238651
Title :
Efficient implementation of 8-bit vedic multipliers for image processing application
Author :
Vijayan, Aravind E. ; John, Arlene ; Sen, Deepak
Author_Institution :
Mechatron./Robot. Lab., Nat. Inst. of Technol., Calicut, India
fYear :
2014
fDate :
27-29 Nov. 2014
Firstpage :
544
Lastpage :
552
Abstract :
Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.
Keywords :
digital arithmetic; field programmable gate arrays; image processing; Vedic mathematics; Vedic multiplier; Xilinx ISim simulator; Xilinx Virtex 4 based FPGA board; comparative analysis; field programmable gate array; image processing application; propagation delay; Computer architecture; Convolution; Delays; Image processing; Random access memory; Synchronization; Convolution; FPGA; Image Processing; Multiplier; Vedic Mathematics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Contemporary Computing and Informatics (IC3I), 2014 International Conference on
Conference_Location :
Mysore
Type :
conf
DOI :
10.1109/IC3I.2014.7019675
Filename :
7019675
Link To Document :
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