Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node

Author

Uchi, S.O. ; Liu, Y.X. ; Masahara, M. ; Tsutsumi, T. ; Endo, K. ; Nakagawa, T. ; Hioki, M. ; Sekigawa, T. ; Koike, H. ; Suzuki, E.

Author_Institution

Nanoelectronics Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Ibaraki

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

4

Abstract

A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided

Keywords

MOSFET; logic circuits; low-power electronics; nanotechnology; 32 nm; 4T-DGFET logic; LSTP; TCAD mixed mode; four-terminal double-gate MOSFET; logic system; low-standby-power; nanotechnology node; power consumption suppression; scaling strategy; threshold-voltage control function; Anisotropic magnetoresistance; Control systems; Delay; Double-gate FETs; Energy consumption; Logic design; Logic devices; Nanoelectronics; Threshold voltage; Voltage control; 4T-DGFET; TCAD mixed mode and LSTP; fin; threshold voltage control technique;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on

Conference_Location

Padova

Print_ISBN

1-4244-0097-X

Type

conf

DOI

10.1109/ICICDT.2006.220801

Filename

1669388