DocumentCode :
2386541
Title :
Analysis and implications of residual metal on spacer material in the self-align silicide process for VSLI manufacturing
Author :
Smith, Patrick L. ; Hossain, Tim ; Roy, Amiya Ghatak ; Zhao, Jin
Author_Institution :
Adv. Micro Devices Inc., Austin, TX, USA
fYear :
2000
fDate :
2000
Firstpage :
129
Lastpage :
132
Abstract :
We have investigated the effect of rapid thermal annealing (RTA), titanium capping, substrate Ar plasma pre-cleaning and post second RTA stripping on the amount of metal residual on silicon nitride and silicon oxide films during the cobalt (Co) self-aligned silicidation process. If our standard silicide process was used, low levels (Detection limit E10 cm-2) of Co were retained regardless of substrate and process conditions. Increasing RTA temperature of Co films that have not been capped with titanium (Ti) had relatively high uniform concentration levels throughout the annealing range. If the Co films are Ti capped the Co decreased in concentration with an increasing annealing temperature. The Ti retention however started several orders of magnitude higher than that of Co and increased slightly with increasing temperature. Pre-cleaning with Ar+ plasma and with aggressive strip led to lower retention of Co and Ti. Undoped silicon oxide was very temperature sensitive and retains more Co than Si3N4 or thermal SiO2 films. Thermal oxide films behave similar to silicon nitride. Chemical bonding data suggest that cobalt combines with silicon, near the surface (>20A). Titanium capping, annealing temperature, free silicon in substrates, chemical strip and film surface conditions are the determining factors for the level of retention. Residual Co and Ti can be nearly eliminated if an additional post RTA wet strip (aggressive) is used, but it must be metered with knowledge that it will be done at the expense of Co silicide removal from poly gate and active regions.
Keywords :
VLSI; bonds (chemical); cobalt; cobalt compounds; dielectric thin films; elemental semiconductors; integrated circuit metallisation; integrated circuit technology; rapid thermal annealing; silicon; silicon compounds; sputter etching; surface cleaning; titanium; 20 A; Ar; Ar plasma; RTA; Si-CoSix-Co-Ti-Si3N4; Si-CoSix-Co-Ti-SiO2; Si3N4; SiO2; VSLI manufacturing; aggressive strip; annealing; annealing temperature; chemical bonding; cobalt self-aligned silicidation process; film surface conditions; post second RTA stripping; pre-cleaning; rapid thermal annealing; residual metal; self-align silicide process; silicon nitride; silicon oxide films; spacer material; substrate Ar plasma pre-cleaning; titanium capping; Annealing; Inorganic materials; Manufacturing processes; Plasma temperature; Semiconductor films; Silicides; Silicon; Substrates; Temperature sensors; Titanium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
ISSN :
1523-553X
Print_ISBN :
0-7803-7392-8
Type :
conf
DOI :
10.1109/ISSM.2000.993632
Filename :
993632
Link To Document :
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