• DocumentCode
    2386568
  • Title

    Comprehensive Simulation of Program, Erase and Retention in Charge Trapping Flash Memories

  • Author

    Paul, Abhijeet ; Sridhar, Ch. ; Gedam, Suny ; Mahapatra, S.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Bombay
  • fYear
    2006
  • fDate
    11-13 Dec. 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A simulator is developed for SONOS flash memories to predict program (P), erase (E) and retention (R) behavior under uniform ID operation. It provides insight on the impact of trap parameters on P, E and R and can be used to optimize memory stacks
  • Keywords
    flash memories; logic simulation; optimisation; SONOS flash memories; charge trapping flash memories; erase simulation; program simulation; retention simulation; simulator; Charge carrier processes; Effective mass; Electron traps; Energy capture; Fabrication; Flash memory; Predictive models; SONOS devices; Scalability; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2006. IEDM '06. International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    1-4244-0439-8
  • Electronic_ISBN
    1-4244-0439-8
  • Type

    conf

  • DOI
    10.1109/IEDM.2006.346793
  • Filename
    4154212
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2386568