Title :
Embedded trench DRAMs for sub-0.10 μm generation by using hemispherical-grain technique and LOCOS collar process
Author :
Saida, Shigehiko ; Sato, Tsutomu ; Sato, Muneharu ; Kito, Masaru
Author_Institution :
Adv. ULSI Process Eng. Dept. IV, Toshiba Corp., Yokohama, Japan
Abstract :
For the future System on Chip era, the embedded DRAM is one of the most important devices. Since the variety of the devices must be produced in small number, it is difficult to reduce the investment cost. Therefore, its suppression is the key. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy realizes 30fF/cell for the 0.08 μm trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 μm trench to 80% of 0.18 μm trench, with a little investment of $1.6M. It is achieved by the LOCOS collar process and HSG technique and so on
Keywords :
DRAM chips; capacitors; costing; integrated circuit economics; oxidation; 0.08 micron; 0.10 micron; 0.18 micron; HSG technique; LOCOS collar process; System on Chip; cost of ownership; embedded DRAM; embedded trench DRAMs; hemispherical-grain technique; investment cost; raw process time; trench capacitor scaling strategy; Capacitance; Capacitors; Costs; Electrodes; Fabrication; Furnaces; High K dielectric materials; High-K gate dielectrics; Investments; Random access memory;
Conference_Titel :
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
0-7803-7392-8
DOI :
10.1109/ISSM.2000.993643
