Impact of Advanced SOI Substrates on Device Architecture and Design

Author

Mazure, Carlos ; Wasselin, Jocelyne

Author_Institution

Soitec S.A., Pare Technologiques des Fontaines, Bernin

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

4

Abstract

The engineering of SOI substrates has allowed for optimization of MOSFET performance while minimizing leakage and parasitic elements. Design innovations have amplified the SOI benefits with a significant reduction of the cost of ownership. To move beyond the 90nm IC node, mobility enhancing strain techniques have been added to the CMOS process. While strained silicon on insulator appears to be a solution for reducing power consumption without affecting the device performance, SOI on high resistivity substrates offers a solution tailored to RF applications. An overview of the advances in Smart Cuttrade engineered substrates will be given, and their impact on device design will be discussed

Keywords

MOSFET; circuit optimisation; integrated circuit design; integrated circuit modelling; semiconductor device manufacture; semiconductor device models; silicon-on-insulator; 90 nm; CMOS process; MOSFET performance optimization; SOI substrates; device architecture; device design; high resistivity substrates; integrated circuit node; leakage elements; mobility enhancing strain techniques; parasitic elements; power consumption reduction; silicon on insulator; CMOS integrated circuits; CMOS process; Capacitive sensors; Conductivity; Costs; Energy consumption; MOSFET circuits; Radio frequency; Silicon on insulator technology; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on

Conference_Location

Padova

Print_ISBN

1-4244-0097-X

Type

conf

DOI

10.1109/ICICDT.2006.220815

Filename

1669402