Critical area based yield modeling on an advanced microprocessor design

Author

Segal, Julie ; Parker, Susan ; Bakarian, Sergei ; Pak, James

Author_Institution

HPL Inc., San Jose, CA, USA

fYear

2000

fDate

2000

Firstpage

191

Lastpage

194

Abstract

Critical area analysis was performed on a complex microprocessor design. (>1 Gbyte GDS file). The following applications of critical area analysis are demonstrated: yield partitioning by process layer, yield partitioning by layout block, and design for manufacturability. Advanced features such as netlist extraction, layer shift operation, and geometric expansion compared to Monte Carlo critical area extraction are discussed

Keywords

design for manufacture; integrated circuit design; integrated circuit modelling; integrated circuit yield; integrated memory circuits; microprocessor chips; 1 Gbyte; Monte Carlo critical area extraction; advanced microprocessor design; critical area analysis; critical area based yield modeling; defect related yield loss; design for manufacturability; geometric expansion; layer shift operation; layout block; netlist extraction; process layer; yield partitioning; Bridges; Conductors; Logic arrays; Manufacturing processes; Microprocessors; Monte Carlo methods; Performance analysis; Predictive models; Solid modeling; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on

Conference_Location

Tokyo

ISSN

1523-553X

Print_ISBN

0-7803-7392-8

Type

conf

DOI

10.1109/ISSM.2000.993646

Filename

993646