A Novel DCVS Tree Reduction Algorithm

Author

Kavehie, Omid ; Navi, Keivan ; Nikoubin, Tooraj ; Rouholamini, Mahnoush

Author_Institution

Dept. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

7

Abstract

This paper presents a new method to simplify the implemented functions by differential cascode voltage switch (DCVS) tree using a new levels coupling rule. The rule introduced in the context provides more reduction possibility by changing the designer´s point of view. The proposed algorithm introduces a new approach for DCVS tree network design by making use of this rule and its combination with the former rules. This algorithm exploits ordered binary decision diagram (OBDD) structures to realize DCVS trees. The approach presented, remarkably improves speed and circuit area

Keywords

binary decision diagrams; logic design; logic programming; tree searching; CAD; coupling rule; differential cascode voltage switch; ordered binary decision diagram; structured logic tree; tree reduction; CMOS logic circuits; Design methodology; Input variables; Latches; Logic circuits; Logic design; Rails; Switches; Switching circuits; Voltage; CAD; Structured logic tree; differential cascode voltage switch logic; ordered binary decision diagrams; transistor count;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on

Conference_Location

Padova

Print_ISBN

1-4244-0097-X

Type

conf

DOI

10.1109/ICICDT.2006.220824

Filename

1669411