DocumentCode
2387011
Title
A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications
Author
Post, I. ; Akbar, M. ; Curello, G. ; Gannavaram, S. ; Hafez, W. ; Jalan, U. ; Komeyli, K. ; Lin, J. ; Lindert, N. ; Park, J. ; Rizk, J. ; Sacks, G. ; Tsai, C. ; Yeh, D. ; Bai, P. ; Jan, C.-H.
Author_Institution
Intel Corp., Hillsboro, OR
fYear
2006
fDate
11-13 Dec. 2006
Firstpage
1
Lastpage
3
Abstract
Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve fT/fMAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with fT/fMAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed
Keywords
CMOS integrated circuits; MOSFET; system-on-chip; 238 GHz; 295 GHz; 360 GHz; 420 GHz; 65 nm; CMOS SOC technology; NMOS transistors; PMOS transistors; RF applications; strained silicon transistors; CMOS technology; Capacitance; Cutoff frequency; MOS devices; MOSFETs; Q factor; Radio frequency; Scattering parameters; Silicon; Varactors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location
San Francisco, CA
Print_ISBN
1-4244-0438-X
Electronic_ISBN
1-4244-0439-8
Type
conf
DOI
10.1109/IEDM.2006.346816
Filename
4154235
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