Title :
The role of test structures for yield enhancement and yield ramp-up: an example of adoptive yield enhancement (AYE): n+/p-well junction leakage enhanced the abnormal leakage current of NMOS´s parasitic NPN-BJT
Author :
Doong, Kelvin Yih-Yuh ; Shen, Binson ; Hsieh, Sunnys ; Lin, Sheng-Che ; Hsu, Charles Ching-Hsiang
Author_Institution :
Worldwide Semicond. Manuf. Corp., Shinchu, Taiwan
Abstract :
The yield loss of an 0.25 μm SRAM caused by the n+/p-well junction leakage was characterized and categorized in two areas by physical location: one is located at the gate/drain region, the other is at the corner of shallow trench isolation. For timely and efficient solving and monitoring of the fabrication line, two sets of test structures and corresponding measurement methods were designed for process monitoring and yield screening. Finally, based on the yield learning, we propose a test-structure-based process control and yield monitoring, called Adoptive Yield Enhancement (AYE)
Keywords :
MOSFET; SRAM chips; bipolar transistors; integrated circuit testing; integrated circuit yield; isolation technology; leakage currents; process control; process monitoring; 0.25 micron; MOSFET; NMOS parasitic NPN-BJT; SRAM; abnormal leakage current; adoptive yield enhancement; fabrication line; gate/drain region; monitoring; n+/p-well junction leakage; process monitor; shallow trench isolation; test structures; test-structure-based process control; yield enhancement; yield learning; yield loss; yield monitoring; yield ramp-up; yield screening; Fabrication; Integrated circuit yield; Logic; MOS devices; Monitoring; Process control; Random access memory; Semiconductor device manufacture; Testing; Thermal stresses;
Conference_Titel :
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
0-7803-7392-8
DOI :
10.1109/ISSM.2000.993663