DocumentCode
2387192
Title
Cell-level path allocation in a three-stage ATM switch
Author
Collier, Martin ; Curran, Tommy
Author_Institution
Sch. of Electron. Eng., Dublin City Univ., Ireland
fYear
1994
fDate
1-5 May 1994
Firstpage
1179
Abstract
A method of cell-level path allocation for three-stage ATM switches has previously been proposed by the authors. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described. Both uniform and non-uniform models of output loading are considered. The algorithm requires knowledge of the number of cells requesting each output module from a given input module. A fast method for counting the number of requests is described
Keywords
asynchronous transfer mode; packet switching; telecommunication network routing; telecommunication traffic; cell-level path allocation; input module; output loading; output module; performance; three-stage ATM switch; Asynchronous transfer mode; Clocks; Hardware; Joining processes; Load modeling; Performance evaluation; Routing; Sorting; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 1994. ICC '94, SUPERCOMM/ICC '94, Conference Record, 'Serving Humanity Through Communications.' IEEE International Conference on
Conference_Location
New Orleans, LA
Print_ISBN
0-7803-1825-0
Type
conf
DOI
10.1109/ICC.1994.368916
Filename
368916
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