Title :
Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface
Author :
Shih, Y.H. ; Lai, E.K. ; Hsieh, J.Y. ; Hsu, T.H. ; Wu, M.D. ; Lu, C.P. ; Ni, K.P. ; Chou, T.Y. ; Yang, L.W. ; Hsieh, K.Y. ; Liaw, M.H. ; Lu, W.P. ; Chen, K.C. ; Ku, Joseph ; Ni, F.L. ; Liu, Rich ; Lu, Chih-Yuan
Author_Institution :
Emerging Central Lab, Macronix Int. Co. Ltd, Hsinchu
Abstract :
Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory
Keywords :
interface states; nitridation; random-access storage; rapid thermal processing; semiconductor device reliability; silicon; silicon compounds; Si-SiO2; array-nitride-sealing; enhanced ANS-ONO process; low-energy buried diffusion implantation; multi-bit/cell nitride trapping nonvolatile memory; nitridized interface; rapid thermal nitridation; Annealing; Degradation; Electrons; Failure analysis; Hydrogen; Nonvolatile memory; Oxidation; Silicon compounds; Temperature; Testing;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0438-X
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346824
