1T MEMS Memory Based on Suspended Gate MOSFET

Author

Abele, N. ; Villaret, A. ; Gangadharaiah, A. ; Gabioud, C. ; Ancey, P. ; Ionescu, A.M.

Author_Institution

Lab. of Micro/Nanoelectronic Devices, Ecole Polytechnique Fed. e de Lausanne

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

The design, operation, characterization and scalability of a 1T SG-MOSFET memory cell that combines a MOSFET solid-state device and a microelectromechanical gate electrode, is reported. The proposed SG-MOSFET memory uses the charging of the gate dielectric by direct contact of the conductive gate with the gate insulator during mechanical pull-in, which results in I-V hysteresis. Very low gate leakage and excellent current ratio in programmed logic states are demonstrated. Cycling without significant degradation up to 105 cycles is experimentally shown and the scalability of the cell is explored by simulation

Keywords

MOSFET; leakage currents; micromechanical devices; random-access storage; semiconductor device models; MOSFET memory cell; gate dielectric; gate insulator; leakage current; microelectromechanical gate electrode; Dielectrics and electrical insulation; Electrodes; Gate leakage; Hysteresis; Leakage current; Logic devices; MOSFET circuits; Micromechanical devices; Scalability; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346826

Filename

4154245