Title :
Module optimization modeling with discrete event simulation
Author :
Bachrach, Robert Z. ; Pool, Mark ; Sunkara, Raja ; Pang, Bin
Author_Institution :
Appl. Mater. Inc., Santa Clara, CA, USA
Abstract :
Module optimization modeling with discrete event simulation is described. The models allow the organization of tools and chambers and visualization of the modules in different configurations as well as the analysis of the expected performance relative to parameters. Representative results for a Dep/Etch/Dep module are presented.
Keywords :
circuit optimisation; discrete event simulation; etching; integrated circuit modelling; modules; semiconductor process modelling; Dep/Etch/Dep module; chambers; discrete event simulation; module optimization modeling; semiconductor fabrication; tools; Analytical models; Calendars; Dielectrics; Discrete event simulation; Fabrication; Fault tolerance; Performance analysis; Production facilities; Productivity; Visualization;
Conference_Titel :
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
Print_ISBN :
0-7803-7392-8
DOI :
10.1109/ISSM.2000.993684
