Title :
Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs
Author :
Bera, L.K. ; Nguyen, H.S. ; Singh, N. ; Liow, T.Y. ; Huang, D.X. ; Hoe, K.M. ; Tung, C.H. ; Fang, W.W. ; Rustagi, S.C. ; Jiang, Y. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., Singapore
Abstract :
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; leakage currents; nanowires; silicon; CMOS compatible process; SiGe; gate-all-around MOSFET; leakage current; nanowire array; vertical stacking; Annealing; CMOS technology; Etching; Fabrication; Germanium silicon alloys; MOSFET circuits; Nanoscale devices; Oxidation; Silicon germanium; Wires;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0438-X
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346841
