A monolithic LTE interleaver generator for highly parallel SMAP decoders

Author

Ilnseher, Thomas ; May, Matthias ; Wehn, Norbert

Author_Institution

Microelectron. Syst. Design Res. Group, Univ. of Kaiserslautern, Kaiserslautern, Germany

fYear

2011

fDate

13-15 April 2011

Firstpage

1

Lastpage

4

Abstract

The LTE standard specifies a throughput of 150MBit/s, while the upcoming true 4G LTE Advanced standard will push this throughput to 1 GBit/s. To achieve this throughput while fulfilling the low power requirements of mobile devices, future receiver circuit architectures need to deploy a high internal parallelism. The LTE standard has been designed with this parallelism in mind, using a QPP interleaver inside the turbo code decoder. In this paper we present a novel method to implement the QPP interleaver which significantly reduces power and area of this circuit.

Keywords

CMOS integrated circuits; Long Term Evolution; MMIC; codecs; decoding; interleaved codes; radio receivers; turbo codes; LTE standard; QPP interleaver; future receiver circuit architecture; highly parallel SMAP decoder; mobile device; monolithic LTE interleaver generator; turbo code decoder; Clocks; Computer architecture; Decoding; Generators; Random access memory; Throughput; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Telecommunications Symposium (WTS), 2011

Conference_Location

New York City, NY

ISSN

1934-5070

Print_ISBN

978-1-4577-0162-7

Type

conf

DOI

10.1109/WTS.2011.5960839

Filename

5960839