Title :
Junction Specifications for the 45nm Node
Author :
Taylor, W.J. ; Verret, E.
Author_Institution :
Austin Silicon Technol. Solutions, Freescale Semicond., Austin, TX
Abstract :
As processes are being defined and transistor architectures are being selected for the 45 nm node, the International Technology Roadmap for Semiconductors (ITRS) provides a worthwhile reference for comparing options. In this paper, we discuss those parameters of the ITRS which are related to transistor junctions, from the viewpoint of one selecting a transistor design. Any selection involves tradeoffs, so by addressing how much leeway is expected for the different targets, those selections can be simplified. Along the way, we highlight some interesting contrasts, and present some unique approaches for reaching the targets
Keywords :
bipolar transistors; 45 nm node; ITRS; International Technology Roadmap for Semiconductors; junction specifications; transistor architecture; transistor design; transistor junctions; Annealing; Doping; Electrostatics; Implants; Intrusion detection; Parasitic capacitance; Postal services; Silicon; Voltage control;
Conference_Titel :
Junction Technology, 2006. IWJT '06. International Workshop on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0047-3
DOI :
10.1109/IWJT.2006.220862
