DocumentCode
2388096
Title
Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS
Author
Taylor, W.J., Jr. ; Capasso, C. ; Min, B. ; Winstead, B. ; Verret, E. ; Loiko, K. ; Gilmer, D. ; Hegde, R.I. ; Schaeffer, J. ; Luckowski, E. ; Martinez, A. ; Raymond, M. ; Happ, C. ; Triyoso, D.H. ; Kalpat, S. ; Haggag, A. ; Roan, D. ; Nguyen, J.-Y. ; La,
Author_Institution
Austin Silicon Technol. Solutions, Freescale Semicond., Inc., Austin, TX
fYear
2006
fDate
11-13 Dec. 2006
Firstpage
1
Lastpage
4
Abstract
We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures
Keywords
CMOS integrated circuits; MOSFET; high-k dielectric thin films; low-power electronics; 45 nm; counter-doped PMOS; dual-gate oxide module; gate leakage current density; high-k gate stacks; low power CMOS; single metal gate; CMOS technology; Costs; Electrodes; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; Silicon; Sputter etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location
San Francisco, CA
Print_ISBN
1-4244-0439-8
Electronic_ISBN
1-4244-0439-8
Type
conf
DOI
10.1109/IEDM.2006.346861
Filename
4154280
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