Properties of Si/SiO2Interfaces in Vertical Trench MOSFETs

We report on the study of the Si/SiO₂ interface of vertical U-shaped trench-gated n+ - polycrystalline Si/oxide/Si (UMOS) capacitor gate structure using capacitance-deep level transient spectroscopy (c-DLTS) and capacitance-voltage (CV). The oxide of a UMOS capacitor is three-dimensional-thermally-grown at different temperature 900degC - 1175degC, on sidewall and base of a reactive-ion etched silicon surface. High-density mid-gap Si/SiO₂ interfacial traps (~10¹¹ eV^-1 cm^-2) are observed with both holes and electron trapping. The amphoteric nature of traps is argued to arise from the P_b- dangling Si bond defect center. Moreover, a study of UMOSFET channel region using constant amplitude charge pumping (CP), measurements coupled with electrical stressing of the gate oxide in the Fowler Nordheim (FN) regime, have shown that the oxide edge adjacent to the drain and the oxide/silicon interface therein are the most susceptible regions to damage. SEM revealed non-uniformity in oxide thickness. Finally, enhanced UMOSFETS channel characteristics are observed for rounded-corner trench-bottom geometry in contrast with sharp-corner trench-bottom geometry