Author :
Nii, H. ; Sanuki, T. ; Okayama, Y. ; Ota, K. ; Iwamoto, T. ; Fujimaki, T. ; Kimura, T. ; Watanabe, R. ; Komoda, T. ; Eiho, A. ; Aikawa, K. ; Yamaguchi, H. ; Morimoto, R. ; Ohshima, K. ; Yokoyama, T. ; Matsumoto, T. ; Hachimine, K. ; Sogo, Y. ; Shino, S. ;
Abstract :
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)
Keywords :
CMOS logic circuits; immersion lithography; integrated circuit reliability; low-k dielectric thin films; porous materials; 45 nm; CMOS technology; MOSFET integration scheme; SD diffusion formation; bulk logic platform technology; dual-damascene structure; nFET; pFET; porous low-k BEOL; porous low-k film; ultra high NA(1.07) immersion lithography; Boron; CMOS technology; DSL; Degradation; Large scale integration; Lithography; Logic; MOSFET circuits; Random access memory; Surface-mount technology;
