Title :
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Author :
Narasimha, S. ; Onishi, Kohei ; Nayfeh, H.M. ; Waite, Andrew ; Weybright, M. ; Johnson, Jamie ; Fonseca, C. ; Corliss, Daniel ; Robinson, C. ; Crouse, Michael ; Yang, Dong ; Wu, C.-H.J. ; Gabor, Attila ; Adam, Tijjani ; Ahsan, Ishtiaq ; Belyansky, M. ; Bl
Author_Institution :
IBM Syst. & Technol. Group, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
Abstract :
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
Keywords :
CMOS integrated circuits; Ge-Si alloys; SRAM chips; immersion lithography; low-k dielectric thin films; porous materials; silicon-on-insulator; 1.0 V; 193 nm; 45 nm; SOI CMOS technology; SiGe; activation techniques; back-end wiring delay; dual-stress liner; enhanced strain; functional SRAM; global wiring delay; ground-rule scaling; high-performance FET response; immersion lithography; porous low-k BEOL; porous low-k dielectric; stress memorization; CMOS technology; Capacitive sensors; DSL; Delay; Dielectrics; FETs; Lithography; Random access memory; Stress; Wiring;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0438-X
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346879
