Author :
Josse, E. ; Parihar, S. ; Callen, O. ; Ferreira, P. ; Monget, C. ; Farcy, A. ; Zaleski, M. ; Villanueva, D. ; Ranica, R. ; Bidaud, M. ; Barge, D. ; Laviron, C. ; Auriac, N. ; Cam, C. Le ; Harrison, S. ; Warrick, S. ; Leverd, F. ; Gouraud, P. ; Zoll, S. ;
Abstract :
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported
Keywords :
SRAM chips; consumer electronics; copper; laser beam annealing; low-k dielectric thin films; multimedia systems; 1.1 V; 45 nm; 45-nm technology node; Cu; Cu metal layers; SRAM cells; active power mitigation; co-implanted halos; consumer electronics; laser anneal; low power platform; low power transistors; mask-free strain engineering techniques; third gate oxide; transistor reliability; ultra low k dielectric; wireless multimedia; Annealing; Capacitive sensors; Consumer electronics; Dielectric substrates; Multimedia systems; Power engineering and energy; Power transistors; Random access memory; Reliability engineering; Voltage;
